Cost-effective soft-switching ultra-high step-up DC–DC converter with high power density for DC microgrid application

DC microgrids are integral to smart grids, enhancing grid reliability, power quality, and energy efficiency while enabling individual grid independence. They combine distributed and renewable energy sources, reducing overall energy consumption. High-gain DC–DC converters are crucial for elevating voltages from low-voltage DC sources like solar panels and wind turbines in DC microgrids. This paper introduces a non-isolated DC–DC converter designed to achieve ultra-high step-up (UHSU) voltage conversion utilizing a two-winding coupled inductor (CI). The propounded UHSU configuration achieves a substantial voltage increase by employing low duty cycles and a decreased turn ratio for the CI, resulting in a smaller core size. Moreover, this UHSU circuit incorporates soft-switching capabilities for both power switches and diodes, enhancing its efficiency. By keeping the voltage stress on the switches low, the design minimizes losses and improves overall efficiency. The operational modes are thoroughly analyzed, and comparisons with other topologies are presented to demonstrate the effectiveness of the proffered UHSU circuit. Finally, the performance of the UHSU circuit is validated through the construction and testing of a 150-W laboratory prototype operating at a switching frequency of 50 kHz, with Vin = 20 V and Vout = 300 V.

(2) The voltage stress on the power switches is minimal, allowing for the use of low-voltage-rated switches with decreased on-resistance.This choice helps to mitigate conduction losses and ultimately enhances the total efficiency of the system.(3) The proffered configuration can produce a substantial output voltage with a minimal duty cycle, thereby decreasing the conduction loss of the switches.(4) Utilizing one core in the propounded structure reduces the size and cost of the circuit and enhances the power density.(5) Both power switches and three of the diodes have zero current switching (ZCS), which leads to enhanced efficiency.

Proposed converter and operation modes
The propounded configuration depicted in Fig. 2 illustrates the design of the presented configuration.This configuration includes two switches (S 1 and S 2 ), four capacitors (C 1 -C 3 and C O ), five diodes (D 1 -D 5 ), and a coupled inductor with a two-winding configuration featuring a primary side winding (N P ) and a secondary side winding (N S ).Furthermore, the turns ratio of this coupled inductor is expressed as n = N S /N P , and the coupling coefficient is represented as k = L m /(L m + L k ).The propounded UHSU circuit, operating in continuous conduction mode (CCM), can be segmented into three subintervals, as demonstrated in Fig. 3.The primary waveforms of voltage and current for these components are illustrated in Fig. 4.

First switching subinterval
In this operational mode, both power switches are activated in zero-current-switching, while diodes D 4 and D 5 are forward-biased, and the remaining diodes are in a reverse-biased state.The magnetizing inductor L m charges through the circuit path including V in , C 1 , S 1 , L m , and S 2 , resulting in a linear increase in i Lm .At the same time, capacitor C 2 charges via the loop consisting of C 2 , D 4 , and N S , and capacitor C 3 charges through the circuit path comprising C 3 , N S , and D 5 .Throughout this time interval, the following relationships are maintained according to Kirchhoff 's Voltage Law (KVL). (1)

Second switching subinterval
In this interval, both power switches are turned off, and diodes D 1 and D 2 function under forward-biased conditions with ZCS conditions, while the remaining diodes are off.The magnetizing inductor's current decreases linearly.Capacitor C 1 charges through the circuit loop involving C 1 , D 1 , L m , and D 2 .According to KVL, the relationship governing this mode can be articulated as follows.

Third switching subinterval
In this phase of operation, both power switches remain inactive, and diodes D 1 and D 2 continue conducting in a forward-biased state.Diode D 3 enters conduction with ZCS conditions, while diodes D 4 and D 5 are in a reverse-biased state.The current in inductor L m decreases steadily.Capacitor C 1 charges through the circuit loop comprising C 1 , D 1 , L m , and D 2 .Simultaneously, the output voltage V O is charged through the circuit path involving V in , D 1 , L m , D 3 , C 2 , N S , C 3 , and V O .According to KVL, the relationships governing this mode can be articulated as follows. (3)

Voltage gain calculation
The principle of volt-second equilibrium for the CI can be applied in the following way: The capacitor voltages, obtained from Eqs. ( 12) and ( 13), are outlined below: The formulated representation for the output voltage of the given setup is as follows: Neglecting the CI coefficient (especially for k = 1), the gain in output voltage should be expressed as:

Voltage stresses of semiconductors
The voltage across the circuit switches and diodes in the setup can be delineated as follows:

Average currents of semiconductors
The average currents flowing through the power switches and diodes can be described as follows:

Boundary condition
For the CCM operation of the suggested circuit, the minimum current of the coupled inductor must be more than zero.The minimum current of the CI and iLm can be calculated as: The boundary-normalized CI time constant can be described by employing (26), ( 27), ( 28) and (29).
The depicted converter has the capability to function across different zones, contingent upon Eq. ( 32), as showcased in Fig. 5.

Efficiency calculation
In this section, calculations are performed to assess the conduction and switching losses of the proffered structure with the objective of optimizing its efficiency.To achieve this, factors such as the internal resistances of diodes (r D ), switches (r S ), inductors (r Lm ), capacitors (r C ), as well as the forward voltage drop across diodes (V FD ) and switches (V FS ) are taken into account in determining power losses.Consequently, the conduction losses of switches and diodes are derived as follows: (26)  The computation of switching losses for the power switches and diodes is carried out as follows: The overall power loss of the power switches and diodes, encompassing both switching and conduction losses, is represented as follows: The conduction losses associated with capacitors C 1 , C 2 , C 3 , and C O are determined as follows: (34) Vol:.( 1234567890) www.nature.com/scientificreports/ The overall power loss of the capacitors is represented as follows: The expression for the conduction loss of the magnetizing inductor L m is formulated as follows: The power loss associated with the core of the CI is denoted as follows: The power loss of the coupled inductor core (PC) is measured in W/kg.The coefficients utilized for the core, namely α, β, and k, are known as Steinmetz parameters, and they are often provided by producers for different core materials.The value of the α coefficient can vary between 1 and 2 for ferrite materials (1 ≤ α ≤ 2).based on Faraday's Law, this can be expressed as: The core area, denoted as A c , is specified by manufacturers for different types of magnetic cores.N represents the turn ratio of the CI.Consequently, the peak flux density, denoted as ΔB, for the CI can be determined as follows: The core loss for the CI is represented as P Core = P C M, where M denotes the mass of the coupled inductor core.Hence, with B m = ΔB/2 taken into account, the core loss is formulated as follows: Referencing the book "Transformer and Inductor Design Handbook" authored by Colonel Wm. T. McLyman, the parameters employed to compute core losses include k = 5.597 × 10 − 4, α = 1.43, β = 2.85, B m = 0.1 T, M = 0.088 kg, and f s = 50 kHz.
Therefore, the total power losses for the ultra-high step-up configuration are computed as follows: The efficiency of the proffered circuit (η) is determined as: where P Out represents the output power of the proposed configuration, defined as P Out = V O2 /R O .By referencing Eqs. ( 33) to (60), the analytical efficiency of the propounded circuit can be derived, and the theoretical and experimental efficiencies of the proffered circuit versus output power are graphed in Fig. 6. Figure 7 illustrates the percentage distribution of power loss for each component type, while Fig. 8 provides a breakdown of power loss percentages specifically for conduction losses, switching losses, and core loss of the CI.As seen in Fig. 7, approximately half of the total power loss is attributed to the power switches, mainly due to their conduction losses.In Fig. 8, the switching losses of the diodes and switches, resulting from ZCS condition, are comparatively lower than both the conduction losses and the power loss of the CI core.

Capacitors voltage ripple in boost mode
The capacitors' design characteristics are determined by averaging capacitor currents across all switching subintervals, considering capacitor voltages, duty cycles, allowable fluctuation range  C %, and a prescribed switching frequency of 50 kHz.Consequently, the minimum values for capacitors C 1 to C O can be computed as follows:

Coupled inductor design
The design specifics of the CI rely on several factors, including the average currents flowing through it, the voltage applied across the CI throughout all switching intervals, the duty cycle, the allowable fluctuation range denoted as  L %, and the frequency of switching.Consequently, the minimum value required for the magnetizing inductor can be formulated as follows:

Number of primary and secondary winding turns of coupled inductor
The selected magnitude for the leakage inductor (L k ) is 3 µH.Consequently, the determination of the magnetizing inductor's value can be expressed utilizing the coupling coefficient of the CI as follows: The magnetic core E42/21/15 has been selected for the CI.Consequently, according to the dimensions provided in the core datasheet, the air gaps of the core for the CI can be defined as follows: Through the utilization of Eq. (61), the count of primary winding turns for the CI can be obtained using the subsequent formula: The ratio of turns for the CI, denoted as n = N S /N P , establishes the count of secondary winding turns, which can be articulated as follows:

Small-signal modeling
Each power semiconductor, the coupled inductor, and the capacitors are considered ideal in this analysis.The CI includes parasitic series resistors denoted as r Lm , while the parasitic series resistors of capacitors are labeled as r C .Utilizing the state-space averaging method enables the derivation of both the average model and the smallsignal model.System equations are formulated for all modes, and they are averaged over each commutation time, accounting for the time interval of each mode.Throughout all three switching subintervals, the system equations are expressed as follows: where m = 1, 2, 3.
The control strategy for the presented converter employs the pole placement method, and the small signal model of the circuit is deduced from the state-space averaged model.Through the small signal modeling approach, state variables and control inputs are delineated into two components: fixed ( X, D ) and variable ( x, d).(68) where variable states ( x ), control inputs ( ũ ), and output signals (y) are described as follows: According to the pole placement technique, the poles of the closed loop can be positioned at any suitable location given that the system is fully state-controllable.The controllability matrix of the proffered circuit is articulated as follows: If the rank of C equals 5, which is equivalent to the number of variable states ( x ), then the system is consid- ered fully controllable.Subsequently, two additional integral states are derived as follows: With the inclusion of the new integral states, the state and output equations are reformulated as follows: In the equation provided, r(t) represents the input reference vector, defined as follows: According to Eq. (78), the new matrixes A and B are articulated as follows: The controllability matrix for the system described in Eq. (78) can be defined as follows: If C is established to be complete-rank, the system mentioned in Eq. ( 78) is entirely controllable if the rank of the matrix M is n + m (where n and m represent the number of variable states ( x ) and output signals (y), respectively).Therefore, there exists a matrix K calculated as: (71) www.nature.com/scientificreports/where K x and K q expressed as follows: Substituting (82) in (78) the following equation is: To ensure suitable Gain Margin and Phase Margin values (GM ≥ 10 and 60 ≤ PM ≤ 80), the trial and error method is employed to determine the positions of the closed-loop poles.By following this approach, the bode plot of the control system for the proffered circuit is demonstrated in Fig. 9.As demonstrated in Fig. 9, the gain margin values for the inductor L m exceed 10 (GM (i Lm ) > 10), and the phase margin for the control path (closedloop) of i Lm is 73.6953, which is deemed acceptable.Additionally, Figs. 10 and 11 depict the block diagram of the pole-placement control method and the current regulator loop of the coupled inductor, respectively.

Comparison study
In order to showcase the effectiveness of the proffered circuit, an examination is conducted to compare its performance with that of other configurations.Table 1 outlines the characteristics of the suggested converter alongside alternative configurations, covering aspects such as voltage gain, maximum stress on power switches and diodes, capability for soft switching, component count, nominal power, efficiency, and ability for common ground utilization.Table 1 presents a comprehensive overview of the converters discussed in references [15][16][17][18][19] .The focus of this paper revolves around the UHSU circuit, with voltage gain serving as the primary parameter for comparison.Figure 12 illustrates the variations in voltage gain across different duty cycles for the compared step-up configurations, with the depicted curves derived from the data expressed in Table 1.The results indicate that the suggested circuit outperforms other structures, particularly surpassing the UHSU configurations in references 23,24,26 .However, it's worth noting that the structures in references 15,16 achieve a higher voltage gain per D > 0.4, albeit marginally higher than that of the proposed circuit.Nevertheless, the proposed converter demonstrates superiority across most factors examined in Table 1.
In Table 1, the second column presents the maximum voltage rating of the power switches.The variation of this parameter across different duty cycles is illustrated in Fig. 13.The graph in Fig. 13 highlights that the suggested circuit exhibits superior performance in terms of the maximum voltage stress experienced by the switches  www.nature.com/scientificreports/compared to other configurations.Notably, the voltage across the power switches is considerably low in the suggested circuit, enabling the selection of a smaller inductor for the propounded design.The third column in Table 1 provides information on the maximum voltage stress experienced by the diodes.Figure 14 displays the curve representing the maximum voltage stress on diodes across various duty cycles, considering a turns ratio (n) of 1.5.It is evident from Fig. 14 that the maximum voltage stress observed in the suggested configuration is lower compared to configurations presented in references 16,18,[22][23][24]27,28 .
The fifth column of Table 1 presents the count of switches, diodes, capacitors, inductors, and CIs.Unlike other configurations that typically employ at least two cores, the proposed converter utilizes only one core.This design choice enhances power density and reduces size due to the streamlined use of a single core.The total number of components is also noted in the subsequent column.In the suggested circuit, this count equals or is lower than most UHSU and high step-up circuits (equaling or being less than structures in 15,17,[19][20][21][22][23][24]26,28,29 ). However,it's important to note that the number of components alone may not fully capture the cost and power density metrics, as some converters with a higher component count may have lower costs and higher power densities due to the lower voltage and current ratings of the components.A cost analysis comparing the proposed converter with other structures is outlined in Table 2. Here, it's evident that the cost of the suggested converter is the most economical.The estimated costs of components were sourced from listings on platforms like AMAZON and    2. The determination of the proffered circuit's volume and size distribution is detailed in Table 3. Notably, the CI constitutes a significant portion of the overall volume, followed closely by the capacitors, with the high-voltage side capacitor being the dominant contributor.In contrast, semiconductor devices make a comparatively minor contribution to the overall volume.Additionally, for comparative purposes, the power density is also provided in Table 4.The proposed converter achieves a theoretical power density of 150 W per 40,292.24mm 3 , surpassing that of other circuits.It's worth noting that the cost and power density metrics were calculated for converters sharing component types.In the final column of Table 1, the power, efficiency, and common ground capability of the configurations are discussed.The propounded circuit is constructed for 150 W with an impressive efficiency of 95.47%, outperforming most other structures.Additionally, common ground capability between the input and output is highlighted as crucial, as configurations lacking this capability may be susceptible to electromagnetic interference noises affecting the circuits.Unlike converters found in 15,17,18,20,22 , the proffered structure possesses common ground capability.Comparative analysis reveals the superior voltage gain of the proposed configuration, along with reduced voltage stress on its power switches and diodes, all achieved at a low cost and with high power density.Moreover, owing to the low voltage stress on the power switch, the presented circuit necessitates a smaller inductor.

Experimental results
To validate the theoretical analysis and actual execution of the proffered circuit, an experimental prototype with a power rating of 150 W is constructed.Table 5 outlines the key specifications of the propounded UHSU converter.Figure 15a depicts the measured output voltage and current, which are recorded at 290 V and 0.32 A, respectively.The theoretical output voltage predicted by Eq. ( 14) is approximately 300 V, closely matching the experimental result.This alignment validates the operation of the proffered circuit.Figure 15b,c display the voltage across capacitors C 1 , C 2 , and C 3 , measured at 38 V and 87 V, respectively.Theoretical calculations based on Eqs. ( 12) and ( 13) predict capacitor voltages of 40 V for C 1 and 90 V for C 2 and C 3 .Figure 16a presents the voltage across power switch S 1 and the corresponding current through S 1 , which were measured at 37 V and 10 A, respectively.Additionally, ZCS on switch S 1 is depicted in the same figure.In Fig. 16b    The proposed converter was tested under various load conditions and input values.In Fig. 18a, the output voltage of the converter initially registers around 290 V with a power output of about 150 W. When the load is suddenly altered and the output power is adjusted to 500 W, the output voltage remains relatively stable after brief transient fluctuations.The output voltage deviates only slightly from the reference value, demonstrating the stability of the closed-loop system in maintaining the output voltage close to the target.Figure 18b depicts the output voltage response when the input voltage suddenly drops from 20 to 16 V.It is evident from Fig. 18b that the output voltage shows minimal variation in response to the input change.

Conclusions
This paper introduces a non-isolated UHSU DC-DC circuit employing the CI method.The proffered UHSU configuration achieves an elevated voltage gain by increasing the turn ratio of the CI.Key merits of the proffered configuration include a high voltage gain with high efficiency, zero current switching of power switches and diodes during the ON-state, minimal voltage stress across semiconductor components, and the flexibility provided by two control parameters for adjusting the circuit's voltage gain (duty cycle and turns-ratio of the CIs).Additionally, the configuration is capable of generating high output voltage with a reduced duty cycle, thereby minimizing conduction losses in the switches.Furthermore, the proposed design offers high power density and cost-effectiveness.The suggested UHSU configuration offers a practical answer for converting low DC to high DC in DC microgrid application.
25) I D3 = I D4 = I D5 = I O www.nature.com/scientificreports/Normalized CI time constant can be expressed as:

Fig. 6 .
Fig. 6.The theoretical and experimental efficiency of the proffered step-up configuration versus output power.

Fig. 8 .
Fig. 8. Calculated power loss percentages for conduction losses, switching losses, and core loss of the coupled inductor (P O = 150W, V in = 20 V and Vo = 300 V).

Fig. 15 .
Fig. 15.The experimental waveforms of output port and capacitors, (a) voltage and current of the output port, (b) voltage across the capacitor C 1 , (c) voltage across the capacitors C 2 and C 3 .

Fig. 16 .Fig. 17 .Fig. 18 .
Fig. 16.The experimental waveforms of power switches and diode D 1 , (a) voltage and current of the power switch S 1 , (b) voltage and current of the power switch S 2 , (c) voltage and current of the diode D 1 .

Fig. 17a .
Fig.17a.Under ZCS condition, diode D 3 exhibits forward bias, registering a voltage of 180 V and a current of 1.7 A, as seen in Fig.17b.The voltage and current profiles of diodes D 4 and D 5 mirror each other, as shown in Fig.17c,d respectively, with measurements indicating 140 V and 1.4 A. Overall, Figs. 15, 16 and 17 collectively demonstrate that the experimental outcomes of the proffered converter closely correspond with the theoretical predictions derived from analysis, thus validating the converter's performance.The proposed converter was tested under various load conditions and input values.In Fig.18a, the output voltage of the converter initially registers around 290 V with a power output of about 150 W. When the load is suddenly altered and the output power is adjusted to 500 W, the output voltage remains relatively stable after brief transient fluctuations.The output voltage deviates only slightly from the reference value, demonstrating the stability of the closed-loop system in maintaining the output voltage close to the target.Figure18bdepicts the output voltage response when the input voltage suddenly drops from 20 to 16 V.It is evident from Fig.18bthat the output voltage shows minimal variation in response to the input change.

Table 2 .
Cost comparison between the proffered configuration and other circuits.

Table 3 .
Power density of the propounded circuit.

Table 5 .
, the voltage and current profiles of switch S 2 are demonstrated, showing a voltage across S 2 of 55 V and a current through S 2 of 11 A. ZCS condition on switch S 2 is also clearly visible in the same figure.Diode D 1 enters conduction under ZCS condition, as shown in Fig. 16c.Voltage and current measurements across diode D 1 indicate values of 38 V and 8 A, respectively.Similarly, diode D 2 displays ZCS condition, with readings of 60 V and 8 A, as depicted in Component characteristic of the implemented circuit.